Split gate flash memory device and method of fabricating the same

ABSTRACT

A split gate flash memory device and method of fabricating the same. A cell of the split gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device andmethod of fabricating the same. More particularly, it relates to a splitgate flash memory device that can achieve high memory cell capacity.

[0003] 2. Description of the Related Art

[0004] Complementary metal oxide semiconductor (CMOS) memory isgenerally categorized into two groups: random access memory (RAM) andread only memory (ROM). RAM is a volatile memory, wherein the storeddata is erased when power is turned off. On the contrary, turning offpower does not affect the stored data in a ROM.

[0005] In the past few years, market share of ROM has been continuouslyexpanding, and the type attracting the most attention has been flashmemory. The fact that a single memory cell is electrically programmableand multiple memory cell blocks are electrically erasable allowsflexible and convenient application, superior to electricallyprogrammable read only memory (EPROM), electrically erasableprogrammable read only memory (EEPROM) and programmable read only memory(PROM). Furthermore, fabricating flash memory is cost effective. Havingthe above advantages, flash memory has been widely applied in consumerelectronic products, such as digital cameras, digital video cameras,mobile phones, notebooks, personal stereos and personal digitalassistants (PDA).

[0006] Since portability of these electrical consumer products isstrongly prioritized by consumers, the size of the products must beminimal. As a result, capacity of flash memory must increase, andfunctions must be maximized while size thereof is continuouslyminimized. Having an increased amount of access data, capacity of memorycells has been enhanced from 4 to 256 MB, and even 1 G byte will becomethe market trend in the near future.

[0007] Hence, there is a need for a flash memory device with high memorycell capacity.

SUMMARY OF THE INVENTION

[0008] Accordingly, an object of the invention is to provide a splitgate flash memory device that can achieve high integration of memorycells thereof.

[0009] Another object of the invention is to provide a method offabricating a split gate flash memory device, wherein the size of memorycells thereof can be reduced.

[0010] Thus, a split gate flash memory cell in accordance with thepresent invention comprises a substrate having a trench therein and aconductive layer disposed on the bottom of the trench. A pair of sourceregions are each disposed in the substrate adjacent to one sidewall ofthe trench and electrically connected by the conductive layer. A sourceisolation layer is disposed on the conductive layer. A pair of tunneloxide layers are each disposed on one sidewall of the trench and on thesource isolation layer. A U-shaped floating gate having a plurality ofinside tips is disposed on the source isolation layer and contacts thetunnel oxide layers thereby. An inter-gate dielectric layer is disposedon the U-shaped floating gate. A control gate is disposed on theinter-gate dielectric. A conductive stud is disposed on the control gateand a drain region disposed in the substrate adjacent to the trench.

[0011] Furthermore, the method of fabricating the split gate flashmemory cell in accordance with the present invention comprises providinga substrate, forming a plurality of parallel long trenches along a firstdirection in the substrate, forming a conductive layer and a pair ofsource regions on the bottom of each long trench, wherein the sourceregions are respectively disposed in the substrate adjacent to twosidewalls of each long trench and electrically connected by theconductive layer therein, forming a source isolation layer on eachconductive layer, forming a tunnel oxide on two sidewalls of each longtrench, forming a U-shaped floating gate with a plurality of inside tipsand a connecting oxide layer therein on each source isolation layer,forming an inter-gate dielectric layer on each U-shaped floating gateand the connecting oxide layer therein, forming a control gate on eachinter-gate dielectric layer, forming a conductive stud on each controlgate, forming a plurality of parallel shallow trench isolation (STI)regions along a second direction, defining a plurality of cell trenches,and forming a drain region in the substrate adjacent to each celltrench.

[0012] In the present invention, the trench-type split gate flash memorydevice disposed in cell trenches within a substrate can achieve higherintegration of memory cell capacity than that in the Prior Art.

[0013] In addition, most of the fabricating processes in the inventionare self-aligned and additional lithography processes and number ofmasks for the whole fabricating process can be reduced. The complexityof fabricating thereof is thus reduced and can be easily achieved.

[0014] Furthermore, most patterns of the masks for fabricating thestacked gate flash memory device are rectangular and can be easilyfabricated. The costs of mask fabrication can be reduced and resolutionlimitations by the photolithography tools can be reduced.

[0015] A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

[0017]FIG. 1 is schematic top view of split gate flash memory devices ofthe invention;

[0018]FIG. 2a is a schematic top view of corresponding cross-sections inFIG. 3a and FIG. 4a of one embodiment of the invention;

[0019]FIG. 2b is a schematic top view of corresponding cross-sections inFIG. 3k and FIG. 4k of one embodiment of the invention;

[0020]FIG. 3a˜3 m are cross-sections of the fabricating process alongthe A-A′ phantom line in FIG. 1; and

[0021]FIG. 4a˜4 m are cross-sections of the fabricating process alongthe B-B′ phantom line in FIG. 1;

DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention provides a split gate flash memory devicethat can meet demands for increased capacity of memory cells. In FIG. 1,a top view of the split gate flash memory device in accordance with thepresent invention is shown. Structure of individual memory cells isdisposed in the cell trenches (referring to trench 250′) along the A-A′phantom line, between two shallow isolation trench (referring to STI)regions along the B-B′ phantom line.

[0023]FIG. 3a˜3 m and FIG. 4a˜4 m respectively illustrate thecross-sections of a fabricating process along lines A˜A′ and lines B˜B′according to an embodiment of the present invention. Moreover, FIGS. 2aand 2 b also illustrate corresponding top views of the fabricatingprocess.

[0024] First, FIG. 3m illustrates a cross-section of the split gateflash memory cells in accordance with the present invention. A memorycell comprises a trench 250′ disposed in the substrate 200, and aconductive layer 205 disposed on the bottom of the trench 250′. A pairof source regions S are each disposed in the substrate adjacent tosidewalls of the trench 250′. A source isolation layer 207 is disposedon the conductive layer 205. A pair of tunnel oxide layers 208 are eachrespectively disposed on one sidewall of the trench 250′ and the sourceisolation layer 207. A U-shaped floating gate 209 having a plurality ofinside tips is disposed on the source isolation layer 207 and contactsthe tunnel oxide layers 208 thereby. An inter-gate dielectric layer 214is disposed on the U-shaped floating gate 209. A control gate 215 isdisposed on the inter-gate dielectric 214. A conductive stud 217 isdisposed on the control gate 215, and a drain region D is disposed inthe substrate 200 adjacent to the trench 250′.

[0025] In FIGS. 3a and 4 a, a semiconductor substrate 200, for example aP-type silicon substrate, is provided. Next, a pad oxide layer 201 and amask layer 202 are sequentially formed on the substrate 200 and thensequentially defined by subsequent lithography and etching, forming aplurality of long trenches 250 with a depth about 30000 Å to 70000 Å inthe substrate 200. The long trenches 250 are parallel to each otheralong a first direction. This top view is shown in FIG. 2a and the depthof a long trench 250 affects the channel length of each split gate flashmemory cell.

[0026] Next, in FIGS. 3b and 4 b, a conformal bottom insulating layer203 is deposited on mask layer 203 and in the long trench 250. Thematerial of the insulating layer 203, for example, can be silicondioxide. Then materials of a protecting layer 204 are deposited on thebottom insulating layer 230 filling the long trench 250. Material of theprotecting layer 204, for example, can be photoresist. Materials of theprotecting layer 204 are then etched back and recessed to a depth H tothe bottom of the long trench 250. Then the bottom insulating layer 203exposed by the residue protecting layer 203 is removed. Thus, a bottominsulating layer 203 having the same height H as the protecting layer204 is left in the long trench 250.

[0027] In FIGS. 3c and 4 c, the residue protecting layer 204 in the longtrench 250 is then removed by a proper solvent (not shown). Next,conductive materials of a conductive layer 205, for example N-typedopant doped polysilicon, are filled in the long trench 250 and on themask layer 202. Then the conductive materials above the mask layer 202are etched back and the conductive materials in the long trench 250 arerecessed to a depth H′ to the bottom of the long trench 250. Thus, aconductive layer 205 with a thickness H′ is left in the long trench 250.Moreover, a depth difference ΔH between the bottom insulating layer 203and the conductive layer 205 is about 100 Åto 200 Å.

[0028] In FIGS. 3d and 4 d, a source material layer 206′ is formed inthe long trench 250 by sequential deposition, etching and recession ofdoped materials. The doped material of the source material layer 206 canbe, for example, N-type dopant doped silicon dioxide and preferablyphosphorous (P) doped or arsenic (As) doped silicon dioxide formed byLPCVD. Thickness of the source material layer 206 is between 500 Å and1000 Å.

[0029] Next, a thermal annealing process, for example a furnaceannealing process, is performed on drive out dopants (such as arsenic)from the source material layer 206 into the substrate 200 adjacent tothe long trench 250. Thus, a pair of source regions S are respectivelyformed in the substrate 200 and electrically connected by the conductivelayer 205 therebetween.

[0030] In FIG. 3e and FIG. 4e, the source material layer 206 in the longtrench 250 is then removed. Next, a source isolation layer 207 with athickness between 350 Å and 850 Åis formed on the conductive layer 205,and limitation of an electrical connection between the source regions Sis fully achieved by the conductive layer 205 therebelow. The sourceisolation layer 207 is formed by sequential deposition, etch-back, andrecession of insulating materials such as silicon dioxide, for example.Next, a threshold voltage implantation Vt is performed on sidewalls ofthe long trench 250 to adjust the threshold voltage of each memory cell.

[0031] In FIG. 3f and FIG. 4f, a tunnel oxide layer 208 is formed on thetwo sidewalls of the long trench 250. The tunnel oxide layer 208 can be,for example, silicon dioxide formed by thermal oxidation. Next, aconformable floating gate layer 209 is formed on the mask layer 202 andin the long trench 250. Materials of the floating gate layer 209 can be,for example, N-type dopant doped polysilicon formed by LPCVD. Next, aconnecting oxide layer 210 with a thickness between 700 Å and 1500 Å isformed in the long trench 250. The connecting oxide layer 210 is formedby sequential deposition, etch-back, and recession of materials such assilicon dioxide. The connecting oxide layer 210 therein can lower thecoupling ratio between the floating gate and the control gate of theflash memory cells of the present invention.

[0032] In FIGS. 3g and 4 g, portions of the floating gate layer 209exposed by the connecting oxide layer 210 are removed, leaving aU-shaped floating gate layer 209 in the long trench 250 as a floatinggate. Then a conformable floating gate oxide spacer layer 211 is formedon the mask layer 202 and in the long trench 250 and etched, leavingfloating gate oxide spacers 211 covering part of the tunnel oxide 208 onsidewalls of the long trench 250. The conformable floating gate oxidespacer layer 211 is formed by LPCVD, for example. In addition, materialsof the floating oxide spacer layer 211 and the connecting oxide layer210 are the same, such as silicon dioxide here. Thus, during etching ofthe floating gate oxide spacer layer 211, the connecting oxide layer 210is lightly etched and the thickness thereof is also decreased by thedescribed etching. Then a floating gate nitride spacer 212 is formed oneach floating gate oxide space 211 by sequentially depositing aconformable floating gate nitride spacer and etching thereon. Theconformable floating gate nitride spacer layer 212 is formed by LPCVD,for example.

[0033] In FIG. 3h and FIG. 4h, the connecting oxide layer 210 can beetched, for example, by wet etching to further lower a thickness about200 Å to 500 Å thereof by exposure of the floating gate nitride spacers212 and insides of the U-shaped floating gate 209. Next, the insides ofthe U-shaped floating gate 209 are isotropically etched and a pluralityof tips is formed thereon. Thus, in the long trench 250 a U-shapedfloating gate 209 with a plurality of inside tips and a connecting oxidelayer 210 therein is formed on the source isolation layer 207 therein.

[0034] In FIG. 3i and FIG. 4i, the floating gate nitride spacers 212 canbe removed, for example, by wet etching. Then, another protecting layer213 with a thickness between 500 Å and 1100 Å is formed in the longtrench 250. Materials of the protecting layer 213 can be, for example,photoresist (PR). Then wet etching removes the floating gate oxidespacers 211 and portions of the tunnel oxide layers 208 from thesidewall of the long trench 250 using the protecting layer 213 as amasking layer.

[0035] In FIG. 3j and FIG. 4j, the protecting layer 213 is then removedusing suitable solvent. Next, a conformable inter-gate dielectric layer214 formed by LPCVD, for example, can be deposited on the mask layer 202and in the long trench 250. The material of the inter-gate dielectriclayer 214 can be, for example, silicon dioxide. Then a control gatelayer 215 is formed in the long trench 250 having a height slightlylower than that of the surface of the substrate 200 as a control gate.The control gate layer 215 is formed by sequential deposition,etch-back, and recession of materials like N-type dopant dopedpolysilicon formed by LPCVD, for example.

[0036] In FIG. 3k and FIG. 4k, a conformable layer of control gatespacer layer 216 is deposited and then etched by subsequent etching.Thus, a control gate oxide spacer 216 is formed on each sidewall of thelong trench 250. The material of the control gate oxide spacer 216 canbe, for example, silicon dioxide. Next, materials of a conductive stud217 are deposited on the mask layer 202 filling the long trench 250followed by etching. Thus, a conductive stud 217 is formed in the longtrench 250 as a connection of the control gate (referring to the controlgate layer 215) therebelow and a wordline formed by subsequent processes(not shown).

[0037] Next, a plurality of parallel long isolation trenches are formedin the substrate 200 (shown in FIG. 4K) along a second direction,perpendicular to the first direction of the long trenches 250 bysequential lithography and etching. The described etching process stopsat the source isolation layer 207 of the long trench 250 therein and aplurality of trenches 250′ comprising the cell structures is thusdefined in the substrate 200. This top view is shown in FIG. 2b. FIG. 3kshows a cross-section along the A-A′ line where the trenches comprisingcell structures are located and FIG. 4k shows a cross-section along theB-B′ where follow-up shallow trench isolation (STI) regions are located.

[0038] In FIG. 31 and FIG. 41, materials of an insulating layer 218 arefilled in the described long isolation trenches. The insulating materialcan be, for example, silicon dioxide formed by high density plasmachemical vapor deposition (HDP CVD).

[0039] In FIG. 3m and FIG. 4m, a planarization process is then performedon level the wafer using the mask layer 202 as a polishing stop layer,leaving an insulating layer 218 therein and the shallow trench isolation(STI) region is thus formed. Next, the mask layer 202 is removed by, forexample, wet etching, and the pad oxide layer 201 therebelow is exposed.Then a drain implantation (not shown) is performed on implant N-typeimpurities such as phosphorous (P) or arsenic (As) ions into thesubstrate 200. Then a thermal annealing process (not shown), for examplea rapid thermal annealing (RTP) process, is performed and drain regionsD are thus respectively formed in the substrate 200 adjacent to eachtrench 250′. Then the pad oxide layer 201 is removed and a secondinsulating layer 219 is formed on each drain region D. The secondinsulating layer 219 is formed by sequential deposition andplanarization of materials of the second insulating layer 219. After theplanarization, the wafer surface is leveled and the conductive stud 217is thus exposed.

[0040] In FIG. 1, a top view illustrating possible follow-up wordline BLand bitline WL is shown. In FIG. 1, the conductive studs 217 within thecell trenches (referring to trench 250′) are further connected by theinterconnecting hypothesis wordlines WL and hypothesis bitlines BL inphantom structures. In addition, the bitlines BL can also connect thedrain regions D therebelow by a proper contact window (not shown) andthe split gate flash memory devices are thus formed.

[0041] Compared with the flash memory cell of the Prior Art, the presentinvention has the following advantages.

[0042] First, cells of the flash memory device in accordance with theinvention are trench-type split gate flash memory device, disposed incell trenches within a substrate rather than those normally disposed onthe surface of a substrate in the Prior Art. Memory cell design of theinvention can thus achieve higher integration capacity than that in thePrior Art.

[0043] In addition, most of the fabricating processes in the inventionare self-aligned. Thus, additional lithography processes and the numberof masks for the whole fabricating process can be reduced. Thecomplexity of fabricating the split gate flash memory device of thepresent invention is reduced and can be easily achieved.

[0044] Second, cells of the split gate flash memory device of thepresent invention are formed into the substrate. Thus, the size of eachflash memory cell is minimized and the integration of the memory cellincreased, allowing capacity of a flash memory device to be increasedand the current within a cell also increased by enlarging the depth ofthe cell trench. Furthermore, most patterns of the masks for fabricatingthe stacked gate flash memory device are rectangular and can be easilyfabricated. The costs of mask fabrication can be reduced as canresolution limitations by photolithography tools.

[0045] While the invention has been described by way of example and interms of the preferred embodiments, it is to be understood that theinvention is not limited to the disclosed embodiments. To the contrary,it is intended to cover various modifications and similar arrangements(as would be apparent to those skilled in the art). Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

1-11. (canceled)
 12. A method of fabricating split gate flash memorycells, comprising the steps of: providing a substrate; forming aplurality of parallel long trenches along a first direction in thesubstrate; forming a conductive layer and a pair of source regions onthe bottom of each long trench, wherein the source regions arerespectively disposed in the substrate adjacent to two sidewalls of eachlong trench and electrically connected by the conductive layer therein;forming a source isolation layer on each conductive layer; forming atunnel oxide on two sidewalls of each long trench; forming a U-shapedfloating gate with a plurality of inside tips and a connecting oxidelayer therein on each source isolation layer; forming an inter-gatedielectric layer on each U-shaped floating gate and the connecting oxidelayer therein; forming a control gate on each inter-gate dielectriclayer; forming a conductive stud on each control gate; forming aplurality of parallel shallow trench isolation (STI) regions along asecond direction, defining a plurality of cell trenches; and forming adrain region in the substrate adjacent to each cell trench.
 13. Themethod as claimed in claim 12, wherein the first direction isperpendicular to the second direction.
 14. The method as claimed inclaim 12, wherein the substrate is P-type silicon substrate.
 15. Themethod as claimed in claim 12, further comprising before forming aplurality of parallel long trenches along a first direction in thesubstrate, the step of sequentially forming a pad oxide layer and a masklayer on the substrate.
 16. The method as claimed in claim 15, whereinthe mask layer is silicon nitride.
 17. The method as claimed in claim15, wherein the pad oxide layer is silicon dioxide.
 18. The method asclaimed in claim 12, further comprising before forming a conductivelayer and a pair of source regions on the bottom of each long trench,the step of forming a bottom insulating layer on the bottom of each longtrench.
 19. The method as claimed in claim 12, wherein forming aconductive layer and a pair of source regions on the bottom of each longtrench further comprises the steps of: forming a source material layerin each long trench; performing a high temperature annealing process,driving out dopants in the source material layer, forming a pair ofsource regions in the substrate adjacent to two sidewalls of each longtrench, electrically connected by the conductive layer therebetween; andremoving the source material layer from each long trench.
 20. The methodas claimed in claim 19, wherein the source material layer is N-typedoped silicon dioxide.
 21. The method as claimed in claim 20, whereinthe N-type doped silicon dioxide comprises phosphorous (P) doped silicondioxide or arsenic (As) doped silicon dioxide.
 22. The method as claimedin claim 12, further comprising before forming a tunnel oxide on twosidewalls of each long trench, performing a threshold voltageimplantation on the sidewalls of each long trench.
 23. The method asclaimed in claim 12, wherein forming a U-shaped floating gate with aplurality of inside tips and a connecting oxide layer therein on thesource isolation layer further comprises: conformably depositing afloating gate layer in each long trench; forming a connecting oxidelayer on the floating gate layer in each long trench; removing portionsof the floating gate layer exposed by the connecting oxide layer,forming a U-shaped floating gate with the connecting oxide layertherein; forming a floating gate oxide spacer on sidewalls of each longtrench; forming a floating gate nitride spacer on the floating gateoxide spacer; partially etching the connecting oxide, exposing part ofthe inside U-shaped floating gate; isotropically etching the insideU-shaped floating gate, forming a plurality of tips on the insidesthereof; and removing the floating gate oxide spacers, the floating gatenitride spacers, and part of the tunnel oxides adjacent to the sidewallsof each long trench, leaving a U-shaped floating gate with a pluralityof inside tips and a connecting oxide layer therein.
 24. The method asclaimed in claim 23, wherein the method for partially etching theconnecting oxide is wet etching.
 25. The method as claimed in claim 12,further comprising before forming a conductive stud on the control gate,the step of forming control gate spacers on sidewalls of each longtrench.
 26. The method as claimed in claim 25, wherein the control gatespacer is silicon dioxide.
 27. The method as claimed in claim 12,wherein forming a plurality of parallel shallow trench isolation (STI)regions along a second direction, and defining a plurality of celltrenches further comprises: sequentially performing a photolithographyprocess and an etching process, defining a plurality of parallel longisolation trenches along a second direction, stopping at the sourceisolation layer therein; and forming an insulating layer in the longisolation trenches.
 28. The method as claimed in claim 27, wherein theinsulating layer is silicon dioxide.
 29. The method as claimed in claim27, wherein the method of forming the insulating layer is high densityplasma enhanced chemically vaporization deposition (HDP CVD).
 30. Themethod as claimed in claim 12, wherein forming a drain region in thesubstrate adjacent to each of the cell trenches further comprises:removing the mask layer, exposing the pad oxide layer; performing adrain implantation; performing a thermal annealing process, forming adrain region in the substrate adjacent to each cell trenches; removingthe pad oxide layer; and forming a second insulating layer on each drainregion.
 31. The method as claimed in claim 30, wherein impurities usedin the drain region implantation are N-type impurities.
 32. The methodas claimed in claim 31, wherein the N-type impurities are phosphorous(P) ions or arsenic (As) ions.